Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
The receive and transmit SDRAMs/SGRAMs are each mapped to a memory location of the
microprocessor address space, and the addresses within the RAMs are accessed by an indirect
addressing method. The RX_DRAM_REGISTER is mapped to address 2000000 and
TX_DRAM_REGISTER is mapped to address 3000000. At this address space exists a 16-bit,
read/write register. For all set-up operations and write operations, the microprocessor writes to
this address port. For reading a SDRAM/SGRAM location, writes are initially performed to set up
the read cycles, and then this SDRAM/SGRAM register is read to obtain the value at the desired
SDRAM/SGRAM location.
To perform a SDRAM/SGRAM operation, the corresponding access code (along with the address
and data) is written to the microprocessor address port corresponding to the SDRAM/SGRAM.
The SDRAM/SGRAM controller inside the QRT converts this access code to a SDRAM/
SGRAM access cycle obeying the signaling requirements of the SDRAM/SGRAM.
Access Code
Instruction
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
NO OP
READ BANK 0
WRITE BANK 0
ACTIVE BANK 0
Reserved
READ BANK 1
WRITE BANK 1
ACTIVE BANK 1
Reserved
PRECHARGE
AUTOREF
Reserved
LOAD REG
Reserved
SELF REFRESH
198
PMC [ PMC-SIERRA, INC ]
