S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Pin Name
UP_DMAREQ
Type
Output
Pin No Function
The DMA request (UP_DMAREQ) is asserted when the
Microprocessor Cell Interface (MCIF) contains a cell to be read.
The first read of the MCIF Data register will return the first word of
the cell. UP_DMAREQ is deasserted after the last word of the
cell has been read or an abort has been signaled. The polarity of
UP_DMAREQ is determined by the DMAREQINV bit in the
Microprocessor Cell Interface Configuration register. By default,
UP_DMAREQ is active high.
UP_BUSYB
Output
The UP_BUSYB output is asserted while a microprocessor
initiated access to external SRAM or internal DRAM data is
pending (for internal SRAM accesses, a microprocessor must poll
the appropriate BUSY register bit). The BUSY bit will be
asserted within 20 ns the rising edge of WRB on which the RAM
access is initiated. The UP_BUSYB output is deasserted after
the access has been completed. A microprocessor access to
external SRAM is typically completed within 30 SYSCLK cycles;
an access to internal DRAM is typically completed within 220
cycles. If the STANDBY bit in the Master Configuration is set to
logic 1, the access time is reduced to typically than 10 SYSCLK
cycles for internal accesses and 25 clock cycles for internal
DRAM accesses. The polarity of the UP_BUSYB output is
programmable and defaults to active low.
UP_INTB
UP_RSTB
Output
Input
The Interrupt Request (UP_INTB) output goes low when an
S/UNI-ATLAS-3200 interrupt source is active and that source is
unmasked. UP_INTB returns high when the interrupt is
acknowledged via an appropriate register access. UP_INTB is
an open drain output.
The active low reset (UP_RSTB) signal provides an
asynchronous S/UNI-ATLAS-3200 reset. UP_RSTB is a Schmitt
trigger input with an integral pull up resistor. When UP_RSTB is
forced low, all S/UNI-ATLAS-3200 registers are forced to their
default states.
Miscellaneous (1 pin)
HALFSECCLK
Input
Half-second clock. This signal must pulse once every half
second, in order to correctly perform OAM alarm monitoring,
OAM cell generation, and policing. If the GEN_HALFSECCLK
register bit is set to logic 1 in the Cell Processor Configuration
Register, then the half-second clock may be internally generated
from the 125 MHz SYSCLK input, and the HALFSECCLK input
may be left unused.
IEEE P1149.1 (JTAG) Interface (5 pins)
TCK
Input
The test clock (TCK) signal provides timing for test operations
that can be carried out using the IEEE P1149.1 test access port.
TMS
Input
The test mode select (TMS) signal controls the test operations
that can be carried out using the IEEE P1149.1 test access port.
TMS is sampled on the rising edge of TCK. TMS has an internal
pull up resistor.
Internal
Pull-Up
TDI
Input
The test data input (TDI) signal carries test data into the S/UNI-
ATLAS-3200 via the IEEE P1149.1 test access port. TDI is
sampled on the rising edge of TCK. TDI has an internal pull-up
resistor.
Internal
Pull-Up
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
61
PMC [ PMC-SIERRA, INC ]
