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PM7325-TC 参数 Datasheet PDF下载

PM7325-TC图片预览
型号: PM7325-TC
PDF下载: 下载PDF文件 查看货源
内容描述: S / UNI - ATLAS -3200电信标准产品数据表初步 [S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet Preliminary]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信电路异步传输模式
文件页数/大小: 432 页 / 2222 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet  
Preliminary  
The S/UNI-ATLAS-3200 output interface must behave as an Rx PHY layer device on the  
UTOPIA bus. As a PHY layer device, it responds with the appropriate cell available status when a  
channel address is on the bus, RPU_ADDR. When the Link Layer device (a TM or switch)  
engages a transfer, the S/UNI-ATLAS-3200 must respond by sending the next cell for the channel  
that has been selected. Optionally, the S/UNI-ATLAS-3200 will behave as a single-PHY device,  
ignoring RPU_ADDR. It will service the internal per-PHY cell queues in a weighted round-robin  
fashion controlled by a software-configurable calendar. The calendar is programmed via the  
RxPhy block’s Calendar Address and Data Register, and is described in Section 10.1.7. The  
RxPhy block, assisted by the SDQ block (see below) performs these functions. The RxPhy  
configuration registers may be found in section 11.9.  
10.1.2 Egress Mode with UTOPIA Level 3 Signaling  
In this configuration, the S/UNI-ATLAS-3200 receives traffic from a traffic manager, and  
transmits traffic to a PHY. This traffic consists of ATM cells, transferred using UTOPIA Level 3  
signaling.  
Figure 6 UTOPIA Level 3 Egress Interface  
SRAM Interface  
JTAG  
CELL FLOW  
JTAG Interface  
Packet Bypass  
FIFO  
Cell Processor  
TPU_DAT[31:0]  
Policing, OAM,  
TLU_DAT[31:0]  
TLU_SOC  
TLU_PAR  
TLU_CLAV  
TLU_WRENB  
TLU_ADDR[5:0]  
TLU_CLK  
Statistics,  
TPU_SOC  
TPU_PAR  
TPU_CLAV  
Translation  
UL3  
UL3  
Tx Master  
Tx Slave  
TPU_WRENB  
TPU_ADDR[5:0]  
Interface  
Interface  
Connection Table  
(Embedded  
DRAM)  
TPU_CLK  
Input  
Output  
Microprocessor  
Cell Interface  
(IMCIF)  
Microprocessor  
Cell Interface  
(OMCIF)  
SCI-PHY  
Interface  
SCI-PHY  
Interface  
CPU Interface  
Backward output cell  
interface  
Backward Input Cell  
Interface  
Microprocessor Interface  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-1990553, Issue 4  
65  
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