S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Figure 5 UTOPIA Level 3 Ingress Interface
SRAM Interface
JTAG
CELL FLOW
JTAG Interface
Packet Bypass
FIFO
Ingress Input:
UL3 master or
POS PHY link
layer interface
Ingress Output:
UL3 slave or
Cell Processor
POS PHY phy
layer interface
RLU_DAT[31:0]
RLU_SOC
RLU_PAR
RLU_CLAV
RLU_RDENB
RLU_ADDR[5:0]
RLU_CLK
Policing, OAM,
Statistics,
RPU_DAT[31:0]
RPU_SOC
RPU_PAR
RPU_CLAV
RPU_RDENB
RPU_CLK
Egress Input:
UL3 slave or
Translation
Egress Output:
UL3 master or
POS PHY phy
UL3
UL3
POS PHY link
layer interface
Rx Master
Rx Slave
layer interface
Interface
Interface
Connection Table
(Embedded
DRAM)
RPU_ADDR[5:0]
Input
Output
Microprocessor
Cell Interface
(IMCIF)
Microprocessor
Cell Interface
(OMCIF)
SCI-PHY
Interface
SCI-PHY
Interface
CPU Interface
Backward Output Cell
Interface
Backward Input Cell
Interface
Microprocessor Interface
The S/UNI-ATLAS-3200 input interface must behave as an Rx Link Layer device on the
UTOPIA bus. As a Link Layer device, it controls the address bus, RLU_ADDR, in order to poll
the PHY Layer device to obtain cell available status. Polling is performed in a weighted round-
robin fashion controlled by a software-configurable calendar. Once the Cell Available
information has been collected through polling, port selection is performed using the same
calendar. The calendar is programmed via the RxLink block’s Calendar Address and Data
Register, and is described in Section 10.1.7. The RxLink block can map external PHY addresses
to different internal PHY addresses via a user-programmable port map, as described in Section
10.1.6. The RxLink block, assisted by the SDQ block (see below) performs these functions. The
RxLink configuration registers may be found in Section 11.6.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
64
PMC [ PMC-SIERRA, INC ]
