S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Pin Name
OCIF_CLAV_PTPA
Type
Input
Pin No Function
(A) not used
(B) TLU_CLAV
(B) Cell available. To indicate that space for at least one cell is
available in the PHY’s transmit cell buffer. For back-to-back
transfer to be guaranteed, TLU_CLAV must be asserted at least
5 cycles before the end of the current transfer. The value of
TLU_CLAV is not used between the selection of an new PHYID
and the second cycle after TLU_SOC is presented on the
interface.
(C) not used
(D) TLP_PTPA
(D) Polled PHY packet available. TLP_PTPA is used together
with TLP_ADDR to poll for transmit FIFOs that have room
available. S/UNI-ATLAS-3200 expects that if TLP_PTPA is
asserted in response to TLP_ADDR, then that FIFO can accept
at least one additional burst of 16 32-bit words, in addition to any
burst currently being transferred. S/UNI-ATLAS-3200 will
terminate a burst at an End Of Packet even if a full 16 words
have not been transferred.
TLP_PTPA is expected to be valid in the cycle following the cycle
in which TLP_ADDR was sampled in the PHY.
Backwards Input Cell Interface (21 pins)
SCI-PHY Interface (16-bit UTOPIA Level 1 with routing information prepended to cells). It can act as an Rx Master
(its default, intended for attachment to an S/UNI-ATLAS-3200 Backwards Output Cell Interface) or as a Tx Slave
(used when connecting to a device that is not an S/UNI-ATLAS-3200).
BI_CLK
Input
IBCIF Clock. This clock should run between 40 to 52 MHz to
ensure sufficient throughput on the Backwards Cell Interface.
BI_RRDENB _TCLAV
Output
Receive Read Enable (in BCIF Rx Master mode)/
Transmit Cell Available (in BCIF Tx Slave mode)
In Rx Master mode, this bit is asserted low to read cells from the
interface.
In Tx Slave mode this indicates to the master that a cell is
available in the transmit buffer.
BI_RCLAV _TWRENB
Input
Receive Cell Available (in BCIF Rx Master mode)/
Transmit Write Enable (in BCIF Tx Slave mode)
In Rx Master mode the slave indicates that it has a cell in its
transmit buffer by asserting this signal.
In Tx Slave mode, the master indicates that it is going to transfer
data into the slave device by asserting this signal.
BI_SOC
Input
Start of Cell. Must be asserted when the first word of the cell is
on the data bus.
BI_DAT[15:0]
BI_PAR
Input
Input
16-bit data bus
Parity over BI_DAT[15:0].
Backwards Output Cell Interface (21 pins)
SCI-PHY Interface (16-bit UTOPIA Level 1 with routing information prepended to cells)
BO_CLK
Input
OBCIF Clock. This clock should run between 40 to 52 MHz to
ensure sufficient throughput on the Backwards Cell Interface.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
59
PMC [ PMC-SIERRA, INC ]
