S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
The S/UNI-ATLAS-3200 provides only minimal support for the Time Stamp field option in PM
cells. The default value of all ones is inserted in the Time Stamp field for all generated Fwd PM
cells. Bwd PM cells may contain the time stamp in the received Fwd PM cell if the BCIF is not
full when the Fwd PM cell arrives, and the Copy_FwPM_Timestamp bit is logic 1 in the Cell
Processor Configuration Register.
10.15 Change of Connection State FIFO
As a configurable option, the S/UNI-ATLAS-3200 maintains a FIFO that monitors all
connections for changes of state (i.e. Continuity Check Alarm, AIS Alarm, RDI Alarm, OAM
Failure, and DRAM CRC Error). If a connection has a change of state at some time (e.g. due to
the receipt of an AIS cell, or due to loss of continuity), a copy of the Status field and the 17-bit
connection address will be written into the FIFO.
A maskable interrupt for the FIFO is provided to notify when valid data is in the FIFO, when it is
at least half full, and when it is full.
If the FIFO becomes full, a background process which checks for changes of state will be
suspended. The process will remain suspended until such time as data have been read out of the
FIFO. It is the responsibility of the management software to ensure the FIFO is polled often
enough to ensure the monitoring of changes of state remain compliant to the GR-1248-
CORE Bellcore and ITU-T I.610 standards.
Table 34 Change of State FIFO
Each FIFO is 256 entries deep, and the contents of the FIFO are shown below:
Bit
31:29
28
27
26
Name
Reserved
Segment End Point
End-to-End Point
Segment Flow
Description
If this bit is logic 1, the connection is a segment end-point.
If this bit is logic 1, the connection is an end-to-end point.
If this bit is logic 1, the connection is part of a defined segment
flow.
25
24
DRAM CRC Err
OAM Failure
If this bit is logic 1, then this VC Table entry suffered an error
in the DRAM, and may need to be reinitialized.
This bit becomes a logic 1 if a segment or end-to-end RDI, AIS
or CC condition has persisted for 3.5 0.5 seconds.
OAM_Failure is cleared as soon as no RDI, AIS or CC
condition remains.
23
22
AIS End To End
Alarm
This bit becomes a logic 1 upon receipt of a single end-to-end
AIS cell. The alarm status is cleared upon the receipt of a
single user cell or end-to-end CC cell, or if no end-to-end AIS
cell has been received within the last 2.5 0.5 sec.
This bit becomes a logic 1 upon receipt of a single segment
AIS cell. The alarm status is cleared upon the receipt of a
single user cell or segment CC cell, or if no segment AIS cell
has been received within the last 2.5 0.5 sec. This bit will
only be asserted by connections which have the Segment End
Point or Segment Flow bits set to logic 1.
AIS Segment Alarm
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
129
PMC [ PMC-SIERRA, INC ]
