S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Bit
21
Name
Description
RDI End To End
This bit becomes a logic 1 upon receipt of a single end-to-end
RDI cell. This bit is cleared if no end-to-end RDI cell has been
received within the last 2.5 0.5 sec.
Alarm
20
19
18
RDI Segment Alarm
This bit becomes a logic 1 upon receipt of a single segment
RDI cell. This bit is cleared if no segment RDI cell has been
received within the latest 2.5 0.5 sec.
This bit becomes a logic 1 if no user cell or end-to-end CC cell
has been received within the last 3.5 0.5 sec. This bit is
cleared upon receipt of a user cell, or end-to-end CC cell.
CC End to End
Alarm
CC Segment Alarm
This bit becomes a logic 1 if no user or segment CC cell has
been received within the last 3.5 0.5 sec. This bit is cleared
upon receipt of a user cell or segment CC cell. Segment CC
alarms are declared only if the VC is part of a segment flow
(Segment_Flow = 1) or is a segment end point
(Segment_End_Point = 1)
17
16
Reserved
Reserved
This bit is reserved and should be masked off.
This bit is reserved and should be masked off.
[15:0]
Connection Address This field contains the 16-bit connection address with which
the change of state is associated.
The FIFO contents may be read through the microprocessor port. The microprocessor may read
the COS FIFO, and when the COSVALID bit is asserted, the contents of the COS FIFO are valid.
The FIFO read-pointer is incremented when the Change of Connection State Data register is read
(assuming the FIFO is not empty). When the Change of Connection State Data Register is read,
the COS FIFO BUSY bit is asserted. At this time, the state of the COSVALID bit is undefined.
The BUSY bit will be deasserted 3-5 SYSCLK cycles after the Change of Connection State Data
register is read. At this time, the COSVALID bit will be defined and will indicate whether
subsequent reads are appropriate.
10.16 Count Rollover FIFO
In order to eliminate the need for the microprocessor to periodically poll counts to prevent them
from rolling over or saturating, the S/UNI-ATLAS-3200 provides a 256-entry Count Rollover
FIFO accessible via the microprocessor port. When the Count Rollover FIFO Enable bit is set in
the Cell Processor Configuration register, then the various per-VC, per-PHY, and Performance
Management counts may be configured to generate Count Rollover entries. An entry is made to
the Count Rollover FIFO every time at least one of these counts has its MSB set. Once an entry
has been made to the FIFO, the MSB for that count is cleared. Thus every entry indicates that 215
(for a 16-bit count) or 231 (for a 32-bit count) events have occurred. If the Count Rollover FIFO
becomes full, the MSB remains set until there is room in the Count Rollover FIFO again. The
counter continues to operate normally until it reaches an all-ones state, at which time it saturates.
So long as the Count Rollover FIFO is cleared out before another 215 (or 231) events can occur, no
events will be lost.
One exception is provided for PM counts. Because the 8-bit counts of BIP-16 errors and Lost
Fwd and Bwd PM Cells may roll over frequently, they may be disabled from generating FIFO
entries by setting the Sat_Fast_PM Counts bit to logic 1 in the Cell Processor Configuration
register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
130
PMC [ PMC-SIERRA, INC ]
