RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
In master mode, the SRC_INTF block sources TATM_D, TATM_PAR,
TATM_SOC, and TATM_ENB while receiving TATM_CLAV. The Start-Of-Cell
(SOC) indication is generated coincident with the first word (only 8-bit mode is
supported) of each cell that is transmitted on TATM_D. TATM_D, TATM_PAR and
TATM_SOC are driven at all times. The TATM_ENB signal indicates which clock
cycles contain valid data for the UTOPIA bus. The device will not assert the
TATM_ENB signal until it has a full cell to send and the target device has
activated TATM_CLAV. The TATM_CLAV signal indicates whether the target
device is able to accept cells or not. Only cell level handshaking is supported. If
the target device is unable to accept any additional cells it must deactivate
TATM_CLAV no later than byte 49 of the current cell. No additional cells will be
sent until TATM_CLAV is activated.
In PHY mode, the SRC_INTF block sources RPHY_D[15:0], RPHY_PAR,
RPHY_SOC, and RPHY_CLAV, while receiving RPHY_ENB. The SOC indication
is generated coincident with the first word (8-bit or 16-bit) of each cell that is
transmitted on RPHY_D[15:0]. In PHY mode, the RPHY_D[15:0], RPHY_PAR,
and RATM_SOC signals are driven only when valid data is being sent; otherwise
they are tristated.
In UTOPIA Level 1 PHY mode, RPHY_CLAV is activated whenever a complete
cell is available to be sent. It remains active until the last byte has been read of
the last available complete cell. A cell is sent one cycle after RPHY_ENB goes
low. If RPHY_ENB goes high during the cell transfer, data is not sent each cycle
following one where RPHY_ENB is high.
RPHY_ADD[4:0] is an input and is used only in UTOPIA Level Two mode. Any
bus cycle following one where RPHY_ADD[4:0] matches CFG_ADDR(4:0) in the
UI_SRC_ADD_CFG register, the UI Block will drive RPHY_CLAV. Otherwise
RPHY_CLAV is tri-stated. If, in addition, during the previous cycle RPHY_ENB
was high and it is low in the current cycle, then the device is selected and the
SRC_INTF begins transmitting a cell the next cycle.
Parity is driven on TATM_PAR(RPHY_PAR) whenever TATM_D(RPHY_D[15:0])
is driven. EVEN_PAR will determine whether even parity or odd parity is
generated. Since odd parity is required by the ATM Forum, EVEN_PAR is
intended to be used for error checking only.
The AAL1gator-8 can tolerate temporary de-assertions of
TATM_CLAV/RPHY_ENB), but it is assumed that enough UTOPIA bandwidth is
present to accept the cells that the AAL1gator-8 can produce in a timely manner.
Once the 4-Cell FIFO fills up in the UI, cells will begin filling up in the 8-cell FIFO
in the A1SP block. Anytime the UTOPIA FIFO fills up the T_UTOP_FULL
interrupt will go active in the MSTR_INTR_REG if it is enabled. This FIFO can fill
during normal operation and is not usually an indication of an error. However,
the A1SP FIFO should not normally fill. If they do fill it indicates there is some
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
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PMC [ PMC-SIERRA, INC ]
