RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
enabled in this mode, and, if the RATM_CLAV input signal is asserted, the
SNK_INTF block waits for an RATM_SOC signal from the PHY layer. Once the
RATM_SOC signal arrives, the cell is accepted as soon as possible. The Start-
Of-Cell (SOC) indication is received coincident with the first word (only 8-bit
mode is supported) of each cell that is received on RATM_D. An 8 cell FIFO
allows the interface to accept data at the maximum rate. If the FIFO fills, the
RATM_ENB signal will not be asserted again until the device is ready to accept
an entire cell. The RATM_ENB signal depends only on the cell space and is
independent of the state of the RATM_CLAV signal. The RATM_CLAV signal
indicates whether the target device has a cell to send or not. Only cell level
handshaking is supported.
In PHY mode, the SNK_INTF block receives TPHY_D[15:0], TPHY_SOC, and
TPHY_ENB while driving TPHY_CLAV. The cell available (TPHY_CLAV) signal
indicates when the device is ready to receive a complete cell. In UTOPIA Level
One mode, TPHY_CLAV is always driven.
In UTOPIA Level Two mode, SNK_INTF responds as a single address device.
When responding as a single address, TPHY_CLAV is driven the cycle following
ones in which TPHY_ADDR(4:0) matches CFG_ADDR(4:0) in
UI_SNK_ADD_CFG register. Otherwise TPHY_CLAV is tri-stated. If, in addition
to an address match, during the previous cycle TPHY_ENB was high and it is
low in the current cycle, then the device is selected and the SRC_INTF begins
accepting the cell that is being received.
The SNK_INTF block waits for an SOC. When an SOC signal arrives, a counter
is started, and 53 bytes are received. If a new SOC occurs within a cell, the
counter reinitializes. This means that the corrupted cell will be dropped and the
second good cell will be received. The SNK_INTF block stores the cell in the
receive FIFO. If the receive FIFO becomes full, it stops receiving cells. The
bytes are written to the FIFO with RATM_CLK. RATM_CLK is an input to the
AAL1gator-8. The maximum supported clock rate is 52 MHz.
Parity is always checked and a parity error will cause an interrupt if the
UTOP_PAR_ERR_EN bit is set in the MSTR_INTR_EN_REG.
FORCE_EVEN_PARITY will determine whether even parity or odd parity is
checked. Since odd parity is required by the ATM Forum,
FORCE_EVEN_PARITY is intended to be used for error checking only. If an
error is detected the UTOP_PAR_ERR bit in the MSTR_INTR_REG is set, and
the corresponding enable bit is set in the MSTR_INTR_EN_REG then INTB will
go active. Any cell received with bad parity will still be processed as normal.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
70
PMC [ PMC-SIERRA, INC ]
