RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 5 UI Block Diagram
UTOPIA Interface (UI) Block
UMUX
SRC_INTF
Signals
to/from
each
FF4CELL
MUX
A1SP
block
TX UTOPIA
Interface and
FIFO
Output Logic
Prioritization
and FIFO Input
Logic
TXUTOPIA
SIGNALS
FF3CELL
FF8CELL
Signals
to/from
each
SNK_INTF
DEM
UX
A1SP
block
RX UTOPIA
Interface and
FIFO
RXUTOPIA
SIGNALS
Input Logic
DEMUX and FIFO
Output Logic
UI_REG
9.1.1 UTOPIA Source Interface (SRC_INTF)
The SRC_INTF block (shown in Figure 5) conveys the cells received from the
UMUX block to the UTOPIA interface. Depending on the value of UTOP_MODE
field in the UI_SRC_CFG register, the UTOPIA interface will either act as an
UTOPIA master (controls the write enable signal) or as an UTOPIA PHY device
(controls the cell available signal). As a PHY device, the SRC_INTF can either
be a UTOPIA Level One device, where it is the only device on the UTOPIA bus,
or a UTOPIA Level Two device where other devices can coexist on the UTOPIA
bus. As a master device, the SRC_INTF can only function as a UTOPIA Level
One device.
If 16_BIT_MODE is set in the UI_SRC_CFG register then all 16 bits of the
UTOPIA data bus are used. 16_BIT_MODE must be ‘0’ in UTOPIA master
mode.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
66
PMC [ PMC-SIERRA, INC ]
