RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
9
FUNCTIONAL DESCRIPTION
The AAL1gator-8 is divided into the following major blocks, all of which are
explained in this section:
• UTOPIA Interface Block (UTOPIAI)
• AAL1 SAR Processing Block (A1SP)
• Processor Interface Block (PROCI)
• RAM Interface Block (RAMI)
• Line Interface Block (LINEI)
• JTAG
9.1 UTOPIA Interface Block (UI)
The UI manages and responds to all control signals on the UTOPIA bus and
passes cells to and from the UTOPIA bus and the two Dual A1SP blocks. Both
8-bit and 16-bit UTOPIA interfaces with an optional single parity bit are
supported. Each direction can be configured independently and has its own
address configuration register.
The following UTOPIA modes are supported.
• UTOPIA Level One Master (8-bit only)
• UTOPIA Level One PHY
• UTOPIA Level Two PHY
• Any-PHY PHY
In the sink direction, the UI uses a 8-cell deep FIFO for buffering cells as they
wait to be sent to the A1SP block. In addition, the A1SP contains an 8-cell deep
FIFO. In the source direction, the UI uses a 4-cell deep FIFOs for holding cells
before they are sent out onto the UTOPIA bus. Also, the A1SP contains an 8-cell
deep FIFO. The data flow showing the FIFOs is shown in Figure 4.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
64
PMC [ PMC-SIERRA, INC ]
