RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
When the line is in MVIP-90 mode, as controlled by the MVIP_EN mode bit in
the Low Speed Line Configuration Register, a common active low frame pulse is
used; F0B. This frame pulse is sampled using the falling edge of the 4 MHz C4B
input clock signal.
Note that GEN_SYNC is ignored in this mode. F0B must be externally
generated and must be only one 4 MHz clock cycle wide.
The AAL1gator-8 updates the data provided on TL_SER[n] on every second
falling edge of C4B. The first bit of the next frame is updated on TL_SER on the
falling C4B clock edge for which F0B is also sampled low. 1 is the most
significant bit and 8 is the least significant bit of each octet.
CAS signaling can be transported by passing it during the last nibble of each
time slot.
Figure 114 MVIP-90 Transmit Functional Timing
CTL_CLK (C4B)
TL_SYNC(0) (F0B)
CHAN 31
CHAN 0
TL_DATA(i)
TL_SIG(i)
7
8
1
2
3
4
5
6
7
8
1
2
2
3
4
5
6
7
8
9
C
D
A
B
C
D
B
C
D
A
13.6.2 H-MVIP Timing
In H-MVIP mode two 8 Mbps incoming external links are broken into eight/four
two Mbps internal links, respectively. Also eight/four 2Mbps internal links are
combined into eight 8 Mbps outgoing external lines.
A common active low frame pulse; F0B; is used to indicate the start of a 128 time
slot frame and is shared by all incoming and outgoing lines. The F0B signal is
expected to be driven off the rising edge of C4B and is sampled using the falling
edge of C4B. The sync signal is used to generate internal RLI_FSYNC and
TLI_FSYNC signals for each 2 Mbps link. In addition GEN_SYNC is ignored as
the frame pulse is always externally generated from F0B. Due to pipelining
delays, the sync signals are offset from the start of frame on the internal links.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
327
PMC [ PMC-SIERRA, INC ]
