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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
Figure 118 Transmit H-MVIP Timing, Expanded View  
TLI_CLK(i)  
C4B  
C16B  
F0B  
TL_DATA0(o)  
TLI_FSYNC(o)  
TS126  
TS127  
TS 0  
TS 1  
TS 2  
TS 3  
TS 4  
TS 5  
TS 6  
TS 0, Internal Link 0  
TS 1, Internal Link 0  
TLI_DATA0(i)  
TLI_SIG0(i)  
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
1
4
5
6
7
A
B
C
D
A
B
C
D
A
B
C
RLI_FSYNC1(o)  
TS 0, Internal Link 1  
TS 1, Internal Link 1  
RLI_DATA1(o)  
RLI_SIG1(o)  
3
4
5
6
7
8
1
2
3
4
5
6
7
8
2
3
4
2
5
A
B
C
D
A
B
C
D
A
B
RLI_FSYNC2(o)  
TS 0, Internal Link 2  
2
TS 1, Internal Link 2  
2
RLI_DATA2(o)  
RLI_SIG2(o)  
1
3
4
5
6
7
8
1
3
4
5
6
7
8
1
3
A
B
C
D
A
B
C
D
RLI_FSYNC2(o)1  
TS 0, Internal Link 3  
TS 1, Internal Link 3  
RLI_DATA2(o)1  
RLI_SIG2(o)1  
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
C
D
A
B
C
D
A
B
C
D
13.6.3 DS3/E3 Timing  
In UDF-HS mode there is no structure and the data is sampled using the falling  
edge of RL_CLK as shown in Figure 119. Because of the higher frequency, data  
should be updated using the falling edge of RL_CLK instead of the rising edge,  
which is used in low speed mode. This allows the full clock cycle to be used  
instead of half a clock cycle.  
Figure 119 Receive High-Speed Functional Timing  
RL_CLK(i)  
RL_SER(i)  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL  
331  
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