RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
13.6.2.1
Receive Side Timing.
In H-MVIP mode there is a 16 MHz (C16B) clock that is used to clock in data and
a 4 MHz clock (C4B) which is used to clock in the frame pulse. The falling edge
of C4B is used to clock in F0B. This falling edge also coincides with the start of
reception of the first data bit of the frame. C16B is used by the internal clock
mux logic to generate a 2.048 MHz TLI_CLK signal for each internal local link.
Data is captured on the second rising edge of C16B that occurs for each data bit.
CAS signaling can be transported by passing it during the last nibble of each
time slot.
Figure 115 shows the timing around F0B pulse and the lower two local links
within a group of four. Figure 115 shows an expanded view, including all four
local links within each group of four. All signals prefixed with “RLI_” are internal
signals and are not visible.
Figure 115 Receive H-MVIP Timing, Close-Up View
RLI_CLK(i)
C4B
C16B
F0B
TimeSlot 127, Line 0
TimeSlot 0, Line 0
RL_DATA(i)
RL_SIG(i)
1
2
3
4
5
6
7
8
1
3
4
5
6
7
8
1
2
3
4
5
6
7
2
A
B
C
D
A
B
C
D
A
B
C
RLI_FSYNC0(o)
RLI_MSYNC0(o)
TimeSlot 31, Internal Link 0
TimeS
2
RLI_DATA0(o)
RLI_SIG0(o)
4
2
5
6
7
8
1
A
B
C
D
TimeSlot 31, Internal Link 1
RLI_DATA1(o)
RLI_SIG0(o)1
3
4
5
6
7
8
A
B
C
D
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
328
PMC [ PMC-SIERRA, INC ]
