RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 108 Ext Freq Select Functional Timing
SYSCLK
FREQUENCY
LINE NUMBER
CGC_SER_IN
CGC_SER_VAL
13.6 Line Interface Timing
13.6.1 16 Line Mode
13.6.1.1
Receive Line Timing
In T1 mode, the rising edge of RL_SYNC must coincide with the leading edge of
the F bit. If RL_SYNC is programmed as an MF pulse, then that edge should
also be the leading edge of a multiframe. Al input signals are sampled on the
falling edge of RL_CLK, as shown in the following figure.
Figure 109 and Figure 110 show how the transmitter receives data from the line
interface. These lines typically interface with the receive output portion of the
corresponding framer. The timing parameters are given in the AC timing section.
RL_SYNC is used in structured modes to align the frame and/or multiframe of
the incoming data. RL_SYNC can be configured to be a frame sync or a multi-
frame sync by the value of MF_SYNC_MODE. This input is ignored in
unstructured modes.
In T1 mode the rising edge of RL_SYNC must coincide with leading edge of the
F bit. If RL_SYNC is programmed as a MF pulse then that edge should also be
the leading edge of a multiframe. All input signals are sampled on the falling
edge of RL_CLK. as shown in the following figure.
Figure 109 Receive Line Side T1 Timing(RL_CLK = 1.544 MHz)
RL_CLK(i)
RL_SYNC(i)
CHAN 24, FRAME 24
CHAN 1, FRAME 1
7
8
1
2
3
4
5
6
7
8
F
1
2
3
4
5
6
7
8
RL_DATA(i)
RL_SIG(i)
C
D
A
B
C
D
A
B
C
D
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
324
PMC [ PMC-SIERRA, INC ]
