RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
13.6.2.2
Transmit Side Timing
In H-MVIP mode, on the transmit side, there is a 16 MHz clock (C16B) that is
used to clock out data and a 4 MHz clock (C4B) which is used to clock in the
frame pulse. The falling edge of C4B is used to clock in F0B. This falling edge
also coincides with the start of transmission of the first data bit of the frame.
C16B is used by the internal clock mux logic to generate a 2.048 MHz TLI_CLK
signal for each internal local link.
CAS signaling can be transported by passing it during the last nibble of each
time slot.
Figure 117 shows the timing around F0B pulse and the lower two local links
within a group of four. Figure 117 shows an expanded view, including all four
local links within each group of four. All signals prefixed with “TLI_” are internal
signals and are not visible.
Figure 117 Transmit H-MVIP Timing, Close-up View
TLI_CLK(i)
C4B
C16B
F0B(i)
Timeslot 0, FRAME n
Timeslot 1, FRAME n
TL_DATA(o)
TL_SIG(o)
7
8
1
2
3
4
5
6
7
8
1
3
4
5
6
7
8
1
2
2
C
D
A
B
C
D
A
B
C
D
TLI_FSYNC0(o)
TLI_MSYNC0(o)
Timeslot 1 Line 0
4
TLI_DATA0(i)
TLI_SIG0(i)
1
2
3
5
A
TLI_FSYNC1(o)
TLI_MSYNC1(o)
Timeslot 0 Line 1
1
Timeslot 1 Line 1
2
TLI_DATA1(i)
TLI_SIG1(i)
7
8
3
C
D
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
330
PMC [ PMC-SIERRA, INC ]
