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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
13.6.1.2  
Transmit Line Timing  
Figure 112 and Figure 113, show how the receiver sends data to the line  
interface. These lines typically interface with the transmit input portion of the  
corresponding framer. The timing parameters are given in the AC timing section.  
TL_SYNC is used in structured modes to align the frame and/or multiframe of  
the incoming data. TL_SYNC can be configured to be a frame sync or a multi-  
frame sync by the value of MF_SYNC_MODE. This input is ignored in  
unstructured modes.  
In T1 mode the rising edge of TL_SYNC coincides with leading edge of the F bit.  
If TL_SYNC is programmed as a MF pulse then that edge will also be the leading  
edge of a multiframe. All output signals are driven on the rising edge of TL_CLK.  
as shown in the following figure.  
Figure 112 Transmit Line Side T1 Timing(TL_CLK = 1.544 MHz)  
TL_CLK(i)  
TL_SYNC(i)  
CHAN 24, FRAME 24  
CHAN 1, FRAME 1  
TL_DATA(o)  
TL_SIG(o)  
7
8
1
2
3
4
5
6
7
8
F
1
2
3
4
5
6
7
8
C
D
A
B
C
D
A
B
C
D
In E1 mode the rising edge of TL_SYNC coincides with the leading edge of the  
bit 1 of the first channel within a frame. If TL_SYNC is programmed as a MF  
pulse then that edge should also be the leading edge of a multiframe. All input  
signals are sampled on the falling edge of TL_CLK. as shown in the following  
figure.  
Figure 113 Transmit Line Side E1 Timing(TL_CLK = 2.048 MHz)  
TL_CLK(i)  
TL_SYNC(i)  
CHAN 31, FRAME 16  
CHAN 0, FRAME 1  
TL_DATA(o)  
TL_SIG(o)  
7
8
1
2
3
4
5
6
7
8
1
2
2
3
4
5
6
7
8
9
C
D
A
B
C
D
B
C
D
A
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL  
326  
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