RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 107 Adaptive Data Functional Timing
SYSCLK
ECC_DOUT(3:0)
ECC_LINE(4:0)
SRTS_STBH
A
5
0
4
8
3
0
2
2
1
B
0
ADAP_STBH
13.5 Ext Freq Select Interface
The Ext Freq Select Interface allows an external source to directly select the line
clock frequency from any one of 171 T1 or 240 E1 frequencies centered around
the nominal clock rate. For T1 the legal input values are –83 to 88. For E1 the
legal input values are –128 to 111. Any values outside of this range will be
clamped to these levels. These levels correspond to a +/-200 ppm T1 clock and
a +/- 100 ppm E1 clock.
The External Interface block has two input ports that allow an external source to
control the frequency synthesizers internal to the CGC. These two ports are
CGC_SER_D and CGC_VALID. CGC_SER_D contains the data that selects
one of the 171/240 frequencies and CGC_VALID indicates when this data is
valid. There should be a rising edge of CGC_VALID at the start of each timing
message. And CGC_VALID should go low at the end of each timing message.
CGC_VALID only needs to be deactivated for one cycle between timing
messages. The CGC block decodes the incoming line number and if the
address matches one of its 8 line numbers passes the data on to the appropriate
frequency synthesizer.
Figure 108 below shows an example of where Line 19 is being programmed to
run with the frequency setting of –79 (Two’s complement). See the section on
the Frequency Synthesizer block for a discussion of the different frequency
settings which range from -83 to 88 in T1 mode and –128 to 111 in E1 mode.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
323
PMC [ PMC-SIERRA, INC ]
