RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
12
OPERATION
This section discusses procedures for setting up or configuring different functions
of the AAL1gator-8.
12.1 Hardware Configuration
The AAL1gator-8 can be configured in several different modes. The line mode of
operation needs to be setup from hardware reset and cannot be changed once
the chip is powered up. The line mode is controlled by the LINE_MODE pin.
This pin will determine whether the line interface supports 8 low speed lines or 1
high speed line, or 2/1 H-MVIP bi-directional lines. See the description of the
Line interface for more details.
The UTOPIA interface can also be set up in different modes. Because different
modes require different sides of the bus driving the control signals, the UTOPIA
will power up with all outputs tri-stated. If it is desired at the system level to pull
some of the control signal so that they default to one way or the other upon
power-up, this can be done using weak pull-up or pull-down resistors. The
UTOPIA interface will remain tri-state until the UI_EN bit in the UI_COMN_CFG
register is set.
The AAL1gator-8 can either generate the transmit line clocks internally or use
clocks supplied to its transmit line clock inputs. Because the device does not
know upon power up which mode will be used, there is a TLCLK_OE signal
which can be used to tell the chip to generate clocks or not generate clocks. If
this pin is tied low the chip will not generate a clock until it is configured to source
a clock. If this pin is tied high the chip will use the clock provided on its RL_CLK
pin as it TL_CLK and will drive this clock externally. Note the option to drive
clocks is only available in Direct mode.
12.2 Start-Up
The AAL1gator-8 uses an internal DLL on SYS_CLK to maintain low skew on the
ram interface. When the chip is taken out of hardware reset, the DLL will go into
hunt mode and will adjust the internal SYS_CLK until it aligns with the external
SYS_CLK. The microprocessor should poll the RUN bit in DLL_STAT_REG until
this bit is set.
At this point the entire chip with the exception of the microprocessor interface
and the DLL are in reset. Before any configuration can be done, including
accessing the ram, the chip must be taken out of software reset by clearing the
SW_RESET bit in the DEV_ID_REG. Once taken out of reset, the external RAM
should be cleared to all zeros. At this point, the A1SP block is still in reset
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