RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
because the A_SW_RESET bit in the A_CMD_REG registers is still set. The
UTOPIA interface is disabled and all UTOPIA outputs are tri-stated because the
UI_EN bit in the UI_COMN_CFG register is not set. The line interface is
configured in the mode indicated by the LINE_MODE pin but all internal registers
are in their reset state. The Line Interface is out of reset at this point but will only
be driving data as if all lines and/or queues are disabled.
12.2.1 Line Configuration
There are line interface registers for Direct Mode. These registers should be set
up before the A1SP is taken out of reset.
While the A1SP is in reset the memory mapped registers which contain the line
configuration (LIN_STR_MODE and HS_LIN_REG) can be initialized. Note that
the R_CHAN_2_QUE_TBL registers and R_STATE_0 and R_LINE_STATE
registers cannot be accessed because they are internal and are being held in
reset.
Once the line is initialized and the LIN_STR_MODE and HS_LIN_REG memory
registers are initialized the CMD_ATTN bit in the A_CMD_REG bit can be set so
that the A1SP can read its configuration. The A_SW_RESET bit should remain
set.
See Line Configuration Details below for more details.
12.2.2 Queue Configuration
Once this is complete the A_SW_RESET bit in the A_CMD_REG can be cleared
which will take the A1SP out of reset. The R_CHAN_2_QUE_TBL will then begin
a 640 SYS_CLK cycle initialization, which resets each timeslot to playing out
conditioned data. At this point the queues can be initialized as needed.
12.2.3 Adding Queues
Queues are added by writing to the ADDQ_FIFO with the number of the queue to
be added. See Processor Interface section for more details
12.2.4 Line Configuration Details
This section is intended to be a guide for programmers.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
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