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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
CHANGEI:  
The delay line tap change event register bit (CHANGEI) indicates the  
CHANGE register bit has changed value. When the CHANGE register  
changes from a logic zero to a logic one, the CHANGEI register bit is set to  
logic one. The CHANGEI register bit is cleared immediately after it is read,  
thus acknowledging the event has been recorded.  
ERRORI:  
The delay line error event register bit (ERRORI) indicates the ERROR  
register bit has gone high. When the ERROR register changes from a logic  
zero to a logic one, the ERRORI register bit is set to logic one. The ERRORI  
register bit is cleared immediately after it is read, thus acknowledging the  
event has been recorded.  
INT_SYS_CLKI:  
The reference clock event register bit INT_SYS_CLKI provides a method to  
monitor activity on the reference clock. When the internal SYS_CLK primary  
input changes from a logic zero to a logic one, the INT_SYS_CLKI register bit  
is set to logic one. The INT_SYS_CLKI register bit is cleared immediately  
after it is read, thus acknowledging the event has been recorded.  
SYS_CLKI:  
The system clock event register bit SYSLCKI provides a method to monitor  
activity on the system clock. When the SYS_CLK primary input changes  
from a logic zero to a logic one, the SYS_CLKI register bit is set to logic one.  
The SYS_CLKI register bit is cleared immediately after it is read, thus  
acknowledging the event has been recorded.  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL  
292  
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