RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
12.2.4.1
Mode Selection
The mode of the Line Interface Block is controlled by the LINE_MODE input pin,
which is also readable, by software via a read-only LINE_MODE register. This
pins should be tied to a certain level through initial hardware reset and not be
changed while out of the reset state. This pin also controls the mode of the
entire Line Interface block, so the entire block is either in Direct mode, or H-MVIP
mode.
12.2.4.2
Direct Mode (Low Speed)
The options available in Direct Low Speed Mode are:
• Per line synchronization: Frame or multiframe basis, and internal control or
externally controlled
• Per line format: PMC standard format or MVIP format.
12.2.4.2.1
Synchronization
Synchronization can be configured on a per line basis, and is controlled by the
MF_SYNC_MODE bit in the Low Speed Configuration Register
(LS_Ln_CFG_REG), and the GEN_SYNC bit in the LIN_STR_MODE memory
register for each line.
Synchronization can either be done on a multi-frame basis or a frame basis. If
multi-frame synchronization is required then MF_SYNC_MODE bit for that line in
the LS_Ln_CFG_REG must be set. Otherwise, if frame synchronization or no
synchronization is required then leave MF_SYNC_MODE bit clear as default.
These values should be configured before A1SP software reset is released.
In the receive direction, synchronization is always controlled by the external line
interface. However, in the transmit direction, synchronization can be controlled
from either the local link side or the external line side. Set GEN_SYNC if the
local link side is controlling synchronization. Otherwise, if GEN_SYNC is low,
then the external lines are controlling synchronization or no synchronization is
required.
12.2.4.2.2
Line Format
There are two choices of line format: 1) PMC standard format, and 2) MVIP
format.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
295
PMC [ PMC-SIERRA, INC ]
