RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
The format can be controlled on a per line basis. If MVIP_EN is set in the Low
Speed Configuration Register for that line (LS_Ln_CFG_REG), then the line is in
MVIP-90 mode. Otherwise the line is in PMC standard format.
This value should be configured before A1SP software reset is released.
Note that if a mixture of MVIP-90 lines and non MVIP-90 lines are used then line
0 must be MVIP-90.
If lines are configured in MVIP-90 mode then TL_SYNC0 becomes the F0B input
(125-us frame sync signal) and CRL_CLK becomes the C4B clock (4.096 MHz).
AAL1gator-8 samples F0B on a C4B falling edge, and expects F0B to be exactly
one C4B clock cycle wide, but F0B need not mark every 125 us frame.
AAL1gator-8 samples RL_DATA and RL_SIG at the 3/4 point in the MVIP-90 bit-
period, which is a C4B rising edge. AAL1gator drives TL_DATA and TL_SIG at
the C4B falling edge at the start of the MVIP-90 bit-period.
Set LIN_STR_MODE_n=0x0001 (no CAS) or LIN_STR_MODE_n=0x0003 (with
CAS) for line 0 in A1SP 0, and any other MVIP-90 lines.
12.2.4.3
H-MVIP Mode
In H-MVIP mode synchronization is always controlled from the external interface
and the sync signal is always considered to be a frame synchronization signal.
Therefore MF_SYNC_MODE and GEN_SYNC should be inactive for all lines
when this mode is in use.
When in H-MVIP mode, the line should be configured to be in normal mode, by
clearing MVIP_EN bit in the corresponding LS_Ln_CFG_REG. In the
LIN_STR_MODE register, the following bits should be disabled (value = ‘0’),
LOW_CDV, E1_WITH_T1_SIG, T1_MODE, GEN_SYNC, CLK_SOURCE_TX,
CLK_SOURCE_RX and SRTS_EN.
12.2.4.4
Direct Mode (High Speed)
The HS_LIN_REG in the A1SP control the High Speed functionality. The
CLK_SOURCE_TX and CLK_SOURCE_RX fields in the LIN_STR_MODE
memory register control the clock mode. In high speed mode only “000” (clock is
an input), or “001” (loop timing) modes are permitted.
The A_SW_RESET bit in the A_CMD_REG memory register functions as a
queue reset signal in high speed mode. If the state of LOOPBACK_ENABLE in
TRANSMIT_CONFIG is desired to be changed, the high speed queue must be
reset using the A_SW_RESET bit.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
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PMC [ PMC-SIERRA, INC ]
