RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x84002H: DLL SW Reset Register (DLL_SW_RST_REG)
Bit
Type
Function
Default
15:8
7:0
Unused
X
X
R
TAP[7:0]
Writing to this register performs a software reset of the DLL. A software reset
requires a maximum of 24*256 SYS_CLK cycles for the DLL to regain lock.
During this time the DLLCLK phase is adjusting from its current position to delay
tap 0 and back to a lock position. Check the RUN bit to see when LOCK has
occurred.
TAP[7:0]:
The tap status register bits (TAP[7:0]) specifies the delay line tap the DLL is
using to generate the outgoing clock. When TAP[7:0] is logic zero, the DLL is
using the delay line tap with minimum phase delay. When TAP[7:0] is equal
to 255, the DLL is using the delay line tap with maximum phase delay.
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