RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x84003H: DLL Control Status Register (DLL_STAT_REG)
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
SYS_CLKI
INT_SYS_CLKI
ERRORI
X
X
X
X
X
X
0
CHANGEI
Unused
R
R
R
ERROR
CHANGE
RUN
0
The DLL Control Status Register provides information of the DLL operation.
RUN:
The DLL lock status register bit (RUN) indicates the DLL found a delay line
tap in which the phase difference between the rising edge of Internal
SYS_CLK and the rising edge of external SYS_CLK is zero. After system
reset, RUN is logic zero until the phase detector indicates an initial lock
condition. When the phase detector indicates lock, RUN is set to logic 1.
The RUN register bit is cleared only by a hardware reset or a DLL software
reset (writing to DLL_SW_RST_REG). This bit should be polled when taking
the chip out of reset. No other operations should take place until RUN is set.
CHANGE:
The delay line tap change register bit (CHANGE) indicates the DLL has
moved to a new delay line tap. CHANGE is set high for eight SYS_CLK
cycles when the DLL moves to a new delay line tap.
ERROR:
The delay line error register bit (ERROR) indicates the DLL has run out of
dynamic range. When the DLL attempts to move beyond the end of the
delay line, ERROR is set high. When ERROR is high, the DLL cannot
generate a clock phase which causes the rising edge of internal SYS_CLK to
be aligned to the rising edge of external SYS_CLK. ERROR is set low, when
the DLL captures lock again.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
291
PMC [ PMC-SIERRA, INC ]
