RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 74 Output of E1 Signaling Bits
Line Output Signals During Every Frame
TL_SER
(t imeslots
...
0
1
2
29
30
ABCD
31
)
ABCD
Channel 0
ABCD ABCD
XXXX
Channel 1 Channel 2
ABCD
XXXX Channel 29 XXXX
ABCD
XXXX
Channel 31
XXXX
XXXX
...
...
TL_SIG
Channel30
XXXX - indicates signaling is invalid
Note:
• The AAL1gator-8 treats all 32 timeslots identically. Although E1 data streams
contain 30 timeslots of channel data, 1 timeslot of framing (timeslot 0) and
one time slot that can either be signaling or data (time slot 16), data and
signaling for all 32 timeslots are stored in memory and can be sent and
received in cells.
In high speed only line 0 is used. The Line Interface Block just passes the data
and clock between the external line and the local link. The data is passed as a
clear channel bit stream and data rates are supported up to 52 Mbps.
Note that if a rate > 45 MHz is used, the SYS_CLK needs to be faster than 38.88
MHz. If the line rate is 52 MHz, SYS_CLK must be 45 MHz.
The A1SP should be configured in UDF-HS mode in the HS_LIN_REG memory
register.
9.6.3.1 H-MVIP Block
This section defines how the Line Interface functions in H-MVIP Mode.
The H-MVIP block supports 2 lines in each direction of 8Mbps H-MVIP formatted
data.
In this mode, the H-MVIP block takes each incoming external 8 Mbps H-MVIP
data stream and breaks it into 4 separate local 2Mbps data streams. The bytes
are taken off the bus in round robin fashion and sent to separate 2Mbps links.
In the outgoing direction the H-MVIP block takes each group of four 2Mbps local
links and combines them into one external 8 Mbps H-MVIP data stream.
In H-MVIP mode there is a common 16 MHz clock (HMVIP16CLK) whose every
other rising edge is used to sample data on all external lines in the receive
direction and whose every other falling edge is used to source data on all
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
169
PMC [ PMC-SIERRA, INC ]
