RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
external lines in the transmit direction. There is also a common 4 MHz clock
(HMVIP4CLK) whose falling edge is used to sample the frame pulse. Internally a
2 MHz clock is generated for each link which connects to the A1SP blocks.
A common frame pulse F0B is also used for all external lines. Individual local
link frame pulses are derived from F0B. This signal is always an input.
Signaling is passed through as received and sent with the corresponding data
byte. Signaling format is the same as in Direct Low Speed mode, where the last
nibble of each timeslot carries the CAS signaling bits.
The type of line is selected based on the value of T1_MODE in the
LIN_STR_MODE memory register for each line. For H-MVIP mode T1_MODE
must be off.
The frame structure for H-MVIP lines can be Structured-Frame (SDF-FR) or
Structured-Multi-Frame (SDF-MF) and is determined by the value of
FR_STRUCT[1:0] in the LIN_STR_MODE memory register for each line.
00
01
10
11
Reserved
SDF-FR
not valid in H-MVIP mode
SDF-MF
SDF-FR mode is used when making a structured connection and CAS signaling
is not being transported. SDF-MF mode is used when making a structured
connection and CAS signaling is being transported. If a mixture of CAS and non-
CAS connections are being made on the same line, then put the line in SDF-MF
mode and set R_CHAN_NO_SIG and T_CHAN_NO_SIG in the queue tables for
the connections not carrying CAS.
Because H-MVIP lines all run off the same clock, there is only one mode of
clocking available in this mode. Therefore the CLK_SOURCE values are not
used. The HMVIP16CLK and HMVIP4CLK will always be used and a clock will
be expected on these pins.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
170
PMC [ PMC-SIERRA, INC ]
