RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
The frame structure for E1 and T1 lines can be unstructured-multiline (UDF-ML),
Structured-Frame (SDF-FR) or Structured-Multi-Frame (SDF-MF) and is
determined by the value of FR_STRUCT[1:0] in the LIN_STR_MODE memory
register for each line.
00
01
10
11
Reserved
SDF-FR
UDF-ML
SDF-MF
SDF-FR mode is used when making a structured connection and CAS signaling
is not being transported. SDF-MF mode is used when making a structured
connection and CAS signaling is being transported. If a mixture of CAS and non-
CAS connections are being made on the same line, then put the line in SDF-MF
mode and set R_CHAN_NO_SIG and T_CHAN_NO_SIG in the queue tables for
the connections not carrying CAS.
Several clocking options exist in this mode and are controlled by the value of the
CLK_SOURCE bits in the LIN_STR_MODE register for each line.
In the receive direction, the CLK_SOURCE_RX bit has two possible options. If
this bit is set then the line receives its clock from the CRL_CLK pin. If this bit is
not set then the line receives its clock from the RL_CLKn pin associated with that
line.
In the transmit direction, eight possible options exist and are controlled by the
value of CLK_SOURCE_TX bits in the LIN_STR_MODE memory register for
each line. The eight options are:
000
001
010
Clock is an input on pin TL_CLK[n].
Clock is an input on pin RL_CLK[n] (loop timing mode).
Clock is internally synthesized in the CGC Block as a nominal E1
or T1 clock based on SYS_CLK and the value of T1_MODE. The
clock is output on TL_CLK[n] pin.
011
100
Clock is internally synthesized in the CGC Block based on SRTS.
The clock is output on TL_CLK[n] pin.
Clock is internally synthesized in the CGC Block using the
adaptive algorithm. The clock is output on TL_CLK[n] pin.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
165
PMC [ PMC-SIERRA, INC ]
