RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
10
MEMORY MAPPED REGISTER DESCRIPTION
The Chip SW_RESET state is automatically entered after a hardware reset is
removed, or it can be asserted by setting the SW_RESET bit in the
DEV_ID_REG. (Note memory cannot be accessed while the chip SW_RESET
bit is set.) The A1SP SW_RESET state is automatically entered after a
hardware reset, or chip SW_RESET, or it can be asserted by setting the
A_SW_RESET bit in the A_CMD_REG for that A1SP.
The initial programming for the AAL1gator-8 is performed by loading the external
memory with specified information while the A_SW_RESET bit is set, in the
A_CMD_REG. (and the Chip SW_RESET is inactive) There is a separate
register for each A1SP. After the memory is initialized, the CMD_REG_ATTN bit
should be set so the configuration data can be read. Then A_SW_RESET can be
removed. The device then reads the data structures from memory and enters the
correct operating mode.
Word data structures have the first byte located at the low-byte end of the bus,
which is also the location of the even data bytes (little endian implementation).
Most AAL1gator control structures and all data buffers are stored in the external
SSRAM. SSRAM accesses by the processor require the A[19] input to be equal
to ‘0’. R_STATE_1, and R_LINE_STATE registers in the receive queue table are
mapped to the memory address space but are actually located inside the chip to
improve performance. All memory locations are readable and writable. Although
once processing has begun, writing to some locations is restricted to prevent
corruption of structures or data buffers used by the AAL1gator. Any restricted
locations are designated below.
The remaining registers which are located inside the chip are accessed when
A[19] is high and A[18] is low. See the Normal Mode Register section for
descriptions of all the internal registers.
The address map is as follows:
Table 11 AAL1gator-8 Memory Map
A[19:17]
Description
“000”
“10X”
“11X”
A1SP memory registers
Internal Normal Mode Registers
Test Mode Registers
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