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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
generates a frame pulse or a multi-frame pulse is determined by the value of  
MF_SYNC_MODE in the LS_Ln_CFG_REG register for that line.  
In normal mode (MVIP_EN bit is low in the LS_Ln_CFG_REG register for this  
line), the first time TL_SYNC is sampled high after being low, indicates the  
beginning of a frame or multi-frame. In MVIP-90 mode (MVIP_EN bit is set in  
the LS_Ln_CFG_REG register for this line), the first time TL_SYNC is sampled  
low after being high, indicates the beginning of a frame or multi-frame. For T1  
structured data a frame is completed every 193 bits. For E1 structured data a  
frame is completed every 32 bytes.  
It is not necessary to provide an edge at the beginning of every frame or multi-  
frame. However if a frame or multi-frame pulse is detected on a non-frame or  
non-multi-frame boundary, then the AAL1gator-8 will resync to the new boundary  
and there will be a temporary disruption of data being played out on the line.  
In T1 mode a multi-frame can either be 12 or 24 frames depending on if the line  
is in Super Frame (SF) or Extended Super Frame (ESF) mode. An E1 multi-  
frame is 16 frames long. A special case of E1 mode exists that permits the use  
of T1 signaling with E1 framing. When E1_WITH_T1_SIG is set in  
LIN_STR_MODE and the line is in E1 mode, a multi-frame of 24 frames will be  
used.  
Signaling data is driven for all frames of any multi-frame and will change only on  
multi-frame boundaries. For T1 mode, signaling data may change every 24th  
frame. For E1 mode, signaling may change every 16th frame.  
The signaling nibble is valid for each channel when the last nibble of each  
channel’s data is being driven. See Figure 73 for an example of signaling bits in  
a T1 frame. See Figure 74 for an example of signaling bits in the E1 mode.  
The line interface block just passes the signaling and data bits from the A1SP  
block to the external output pins.  
Figure 73 Output of T1 Signaling Bits  
Line Output Signals During Every  
TL_SER  
1
2
3
...  
22  
ABCD  
23  
ABCD  
24  
(timeslots  
)
ABCD  
XXXX  
Channel 1  
ABCD  
ABCD  
ABCD  
XXXX  
XXXX  
TL_SIG  
XXXX  
...  
XXXX  
XXXX  
...  
Channel 2  
Channel 21  
Channel 22  
Channel 23  
Channel 0  
XXXX - indicates signaling is  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL  
168  
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