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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
101  
110  
Clock is internally synthesized based on values received on the  
CGC interface. (externally controlled) The clock is output on  
TL_CLK[n] pin.The clock on CTL_CLK input pin is used.  
The clock on CTL_CLK input pin is used and signaling data is  
output on TL_CLK[n] pin.  
9.6.2.1.1 Receive Direction  
The Line Interface Block accepts deframed data from the 8 external lines. The  
data, signaling and synchronization signals are received from the external  
interface. The external lines can support data rates up to 15 Mbps per line.  
(However the total aggregate bandwidth cannot exceed 20 Mbps). The falling  
edge of RL_CLK[n] is used to clock in the data and is used as the active edge for  
all receive logic in this mode. For structured data, the Line Interface Block uses  
the external synchronization input signals (RL_SYNC[n]) as either frame pulses  
or multi-frame pulses. Whether the Line Interface Block interprets RL_SYNC as  
a frame pulse or a multi-frame pulse is determined by the value of  
MF_SYNC_MODE in the LS_Ln_CFG_REG register for that line. If the line is  
configured for UDF-ML mode (unstructured), the data will be passed as a clear  
channel bit stream and RL_SYNC[n] will be ignored.  
In normal mode (MVIP_EN bit is low in the LS_Ln_CFG_REG register for this  
line), the first time RL_SYNC[n] is sampled high after being low, indicates the  
first bit of a frame or multi-frame. In MVIP-90 mode (MVIP_EN bit is set in the  
LS_Ln_CFG_REG register for this line), the first time RL_SYNC[n] is sampled  
low after being high, indicates the first bit of a frame. For T1 structured data a  
frame is completed every 193 bits. For E1 or MVIP-90 structured data a frame is  
completed every 32 bytes.  
It is not necessary to provide an edge at the beginning of every frame or multi-  
frame. However if a frame or multi-frame pulse is detected on a non-frame or  
non-multi-frame boundary, then the AAL1gator-8 will resync to the new boundary  
and cell generation will be suppressed for 12 – 32 ms.  
In T1 mode a multi-frame can either be 12 or 24 frames depending on if the line  
is in Super Frame (SF) or Extended Super Frame (ESF) mode. An E1 multi-  
frame is 16 frames long. A special case of E1 mode exists that permits the use  
of T1 signaling with E1 framing. When E1_WITH_T1_SIG is set in  
LIN_STR_MODE and the line is in E1 mode, a multi-frame of 24 frames will be  
used.  
Since signaling is accumulated by the framer over an entire multi-frame,  
signaling only has to be sampled once per multi-frame. The AAL1gator-8 reads  
signaling during the last frame of every multi-frame. If the framer supplies  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL  
166  
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