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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
constant signaling for an entire multi-frame, then the multi-frame sync signal is  
not required unless there is a desire to synchronize the multi-frame with the data  
across the network. In general this is not necessary.  
The AAL1gator-8 reads the signaling nibble for each channel when it reads the  
last nibble of each channel’s data. See Figure 71 for an example of a T1 frame.  
See Figure 72 for an example of an E1 frame.  
Figure 71 Capture of T1 Signaling Bits  
Line Signals During the Last Frame of a  
RL_SER  
1
2
3
...  
22  
23  
ABCD  
24  
(timeslots  
)
ABCD  
XXXX  
Channel 1  
ABCD  
ABCD  
ABCD  
ABCD  
XXXX  
XXXX  
RL_SIG  
XXXX  
...  
XXXX  
XXXX  
...  
Channel 2  
Channel 21  
Channel 22  
Channel 23  
Channel 0  
XXXX - indicates signaling is  
Figure 72 Capture of E1 Signaling Bits  
Line Signals During the Last Frame of a Multiframe  
RL_SER  
(t imeslots  
...  
0
1
2
29  
30  
ABCD  
31  
ABCD  
XXXX  
Channel 31  
)
ABCD  
Channel 0  
ABCD ABCD  
XXXX  
Channel 1 Channel 2  
ABCD  
XXXX Channel 29 XXXX  
XXXX  
XXXX  
...  
...  
RL_SIG  
Channel30  
XXXX - indicates signaling is ignored  
Note:  
AAL1gator-8 treats all 32 timeslots identically. Although E1 data streams contain  
30 timeslots of channel data, 1 timeslot of framing (timeslot 0) and one time slot  
that can either be signaling or data (time slot 16), data and signaling for all 32  
timeslots are stored in memory and can be sent and received in cells.  
9.6.3 Transmit Direction  
In the line transmit direction, for structured data, the Line Interface Block may  
take the TL_SYNC input signal and depending on the value of  
MF_SYNC_MODE interpret the signal as either a frame pulse or multi-frame  
pulse. Alternatively if GEN_SYNC in LIN_STR_MODE memory register is high  
for that line, then the Line Interface Block will take the frame pulse or multi-  
frame pulse generated by the A1SP Block for the local link and output that signal  
to the TL_SYNC[n] pin on the external lines. Whether the Line Interface Block  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL  
167  
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