RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
information a common clock is used, which is shared across all lines. This
option can be configured on a per line basis.
2 Mbps MVIP mode is also supported where the line is handled in
accordance with the MVIP-90 specification. MVIP mode can be individually
selected per line for all 8 lines. Tri-stating of individual time slots is not
supported. There is a common 4 MHz clock and a common framing
reference signal.
Note that if a mix of MVIP-90 and non MVIP-90 lines are being used, line 0
must be MVIP-90.
Line 0 can also be configured to be a highspeed (E3/DS3) line. In this mode,
none of the other lines can be used.
H-MVIP Mode
This mode supports 2 separate 8 Mbps H-MVIP lines with 2 /1in the transmit
direction and 2/1 in the receive direction. There is a common 16 MHz clock,
a 4 MHz clock, and a common framing reference signal. Two Separate data
pins and signaling pins are provided in each direction. Individual time slots
cannot be disabled.
Internally each 8 Mbps stream is converted into four 2 Mbps streams in a
round-robin fashion.
The mode of the module is determined by the value of the LINE_MODE pin. The
following encoding is used:
Table 10 LINE_MODE Encoding
LINE_MODE[0]
Line Interface Mode
“0”
“1”
Direct
H-MVIP
Figure 70 shows the block diagram for the Line Interface Block. The block
consists of the H-MVIP Block and mux/demux logic.
The B0 mux/demux logic selects between the H-MVIP data or external direct
links.
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