RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
The SSRAM interface runs at the same frequency as SYS_CLK and can run up
to 45 MHz.
9.6 Line Interface Block (AAL1_LI)
9.6.1 Conventions
The following conventions are used in this document:
The 8 lines, which connect the AAL1_LI to the A1SP block, are called local
links. The lines on the external interface are called external lines.
The direction from the local links to the external line interface is call the transmit
direction. The direction from the external line interface to the local links is called
the receive direction.
9.6.2 Functional Description
The line interface block is responsible for passing the TDM data between the
A1SP block and converting it to the appropriate protocol used on the external
lines. The options available are:
Direct Mode
This is mainly a pass through mode between the external 8 lines and the 8
local links, which connect to the A1SP block. This mode is used to connect to
any PMC E1 or T1 Framer or compatible device. This mode is also used to
interface to devices, which support the MVIP-90 protocol. 8 lines are
supported, including a clock, data, frame pulse, and signaling pin for each
direction. In addition any low speed (< 2.5 MHz) clear channel data stream
can be passed in this mode.
Note clocks rates up to 15 MHz are supported in this mode. However, the
aggregate bandwidth cannot exceed 20 Mbps. Therefore, if all 8 lines are
used and are the same rate, 2.5 MHz is the highest rate supported. If 4 lines
are used 5 MHz is the highest rate supported.
A common clock pin is also available, which can be shared across all receive
lines or all transmit lines and is selectable on a per line basis.
Some framers also share a clock and signaling pin, where the clock pin
becomes a signaling pin when signaling is required or remains as a clock pin
when individual clocks per line are required. When this pin carries signaling
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
162
PMC [ PMC-SIERRA, INC ]
