PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
As long as HOLDOFF is not high, /SP_ADD_EN, /SP_DATA_EN, and SP_DATA_DIR are acti-
vated at the next clock cycle (3) allowing the microprocessor address and data to pass through the
address and data buffer to the RAM. To minimize bus conflicts when the microprocessor access
follows an AAL1gator II-initiated access, /SP_ADD_EN and /SP_DATA_EN signals are
delayed.
At the next rising edge of SYS_CLK (4), /MEM_CS and /MEM_WE are activated. The /MEM_
WE is delayed to provide sufficient setup time for /MEM_CS and MEM_DATA.
At the following clock cycle (5), /PROC_ACK is activated and /SP_DATA_EN, /SP_ADD_EN,
and /MEM_CS are deactivated. The relative skew of these signals guarantees sufficient hold time.
To eliminate bus contention, a recovery cycle is inserted between the microprocessor access and
any subsequent access. /PROC_ACK is held active until /PROC_CS is deactivated.
Cycles (1) and (2) are grouped together in Figure 71 for the sake of convenience. These are nor-
mally two separate clock cycles.
NOTE: The timing characteristics (indicated by asterisks in the table following Figure 71)
are based on external component requirements.
ꢀꢉꢅ
PMC [ PMC-SIERRA, INC ]
