PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
1, 2
3
4
5
SYS_CLK
PROC_ADD
PROC_DATA
/PROC_CS(i)
/PROC_WR(i)
Tasu17
ADDR17(i)
MEM_ADDR(i)
MEM_DATA(io)
/MEM_CS(o)
Tah
Tdsu
Twd
Tdh
Twd
Tasu
/MEM_WE(o)
/MEM_OE(o)
Tq
Taa
Tcea
/PROC_ACK(i)
/SP_DATA_EN(o)
/SP_ADD_EN(o)
SP_DATA_DIR(o)
Tded
Tded
Taed
Taed
Tddh
NON_PROC READ CYCLE
PROC WRITE CYCLE
RECOVERY CYCLE
NON_PROC CYCLE
Figure 71. Microprocessor RAM Write Cycle Timing
Parameter Signals
Symbol
Min
Max
Unit
Taa
Acknowledge assertion after /PROC_
/PROC_ACK
5
29
SYS_CLK
periods
(See note CS or /PROC_WR; whichever comes
below)
last
Tasu
Address setup to write pulse*
MEM_ADDR, /MEM_WE
10
2
ns
ns
Tcea
/PROC_CS deassertion to /PROC_ACK /PROC_ACK
deassertion
15
25
Twd
Tdsu
Tded
Taed
Tq
Write pulse delay
/MEM_WE
8
15
7
ns
ns
ns
ns
ns
Data setup to write pulse off*
Data enable delay
MEM_DATA
/SP_DATA_EN
/SP_ADD_EN
SP_DATA_DIR
25
20
15
Address enable delay
Clock-to-output delay
5
2
ꢀꢉꢆ
PMC [ PMC-SIERRA, INC ]
