PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Symbol
Parameter
Clock-to-output delay
Clock-to-output delay
Signals
Min
Max
Unit
Tq
Tq
/MEM_CS
2
2
18
18
ns
ns
ns
ns
ns
ns
/PROC_ACK
Tah
Address hold time*
Data hold time*
MEM_ADDR, /SP_ADD_EN
MEM_DATA, /SP_DATA_EN
/SP_DATA_EN, SP_DATA_DIR
ADDR17
5
Tdh
5
Tddh
Tasu17
Data direction delay hold time
Address setup to SYS_CLK
10
2
* These parameters are dependent on external components and assume that the requirements from Table 26 on page 195 are
met.
NOTE: Taa is dependent on the HOLDOFF signal. If HOLDOFF is not asserted when the
access begins, Taa will be a maximum of five SYS_CLK periods. If the access
occurs immediately after another access, then Taa will be 23 to 29 SYS_CLK peri-
ods. Refer to section 6.5.3 “Microprocessor Holdoff Timing” on page 116 for a
description of the HOLDOFF activity.
6.5.2.2 Microprocessor RAM Read Cycle Timing
Figure 72 on page 109 shows the timing for a microprocessor-initiated read cycle. It shows the
two-cycle read operation occurring immediately after a non-microprocessor write cycle. RAM
reading is not honored if higher priority internal functions request the memory, or the holdoff
from a previous microprocessor transfer has not expired. For processor read operations, /SP_
DATA_EN goes active when both /PROC_CS and /PROC_RD are active. /PROC_CS and
/PROC_RD are double sampled (1 and 2) at the rising edge of SYS_CLK; and at (3) ADDR17 is
sampled to distinguish between a command register read and a RAM read.
The /SP_ADD_EN is activated at the next clock cycle (3), as long as HOLDOFF is not high, to
allow the microprocessor address to pass through to the RAM. Also /MEM_CS and /MEM_OE
are activated to enable the RAM. In this case, /MEM_CS was already active due to the access
from the previous cycle. SP_DATA_DIR remains high, allowing RAM data to pass through to the
processor. At this time, SP_DATA_CLK also goes low in preparation of going high in a few
cycles to latch the RAM data into the data latch. The /SP_ADD_EN is delayed to minimize bus
conflicts when the microprocessor access follows a non-microprocessor access. The control sig-
nals remain constant through the next clock cycle (4) allowing the read data to stabilize.
In the following clock cycle (5), /SP_ADD_EN is deactivated and SP_DATA_CLK goes high,
which clocks the RAM data into the data latch. The skew of /SP_ADD_EN guarantees sufficient
hold time for the data to be latched. In the following clock cycle (6), /MEM_CS and /MEM_OE
are deactivated and /PROC_ACK is activated.
ꢀꢉꢇ
PMC [ PMC-SIERRA, INC ]
