PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 1EH: ELST Idle Code
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
The contents of the IDLE CODE register replace the timeslot data in the BRPCM
serial data stream when the framer is out of frame and the TRKEN bit in the E1
Configuration Register is a logic 1. Since the transmission of all ones timeslot
data is a common requirement, the IDLE CODE register is set to all ones when
the CBI reset signal is active. Bit 7 is the first to be transmitted.
The writing of the idle code pattern is asynchronous with respect to the output
data clock. One timeslot of idle code data will be corrupted if the register is
written to when the framer is out of frame.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
121
PMC [ PMC-SIERRA, INC ]
