PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 1CH: ELST Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
ACCEL
Unused
Unused
Unused
Unused
Unused
IR
0
X
X
X
X
X
1
R/W
R/W
OR
1
This register controls the format of the expected input frame to the ELST block
and the format of the generated output frame from the ELST block.
ACCEL:
The ACCEL bit is used for production test purposes only. THE ACCEL BIT
MUST BE PROGRAMMED TO LOGIC 0 FOR NORMAL OPERATION.
IR:
The IR bit selects the input frame format. The IR bit must be set to logic 1 to
properly handle the E1 frame format being input into the ELST. SETTING IR
TO LOGIC 0 IS A RESERVED SETTING AND SHOULD NOT BE USED.
OR:
The OR bit selects the output frame format. The OR bit must be set to logic 1
to properly generate the E1 frame format output from the ELST. SETTING
OR TO LOGIC 0 IS A RESERVED SETTING AND SHOULD NOT BE USED.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
119
PMC [ PMC-SIERRA, INC ]
