PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 1DH: ELST Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
SLIPE
X
X
X
X
X
0
R/W
R
SLIPD
SLIPI
X
X
R
SLIPE:
The SLIPE bit position is an interrupt enable that when set, allows the INT
output to go HIGH when a slip occurs. When the block is reset the SLIPE bit
position is cleared and interrupt generation is disabled.
SLIPD:
The SLIPD bit indicates the direction of the last slip. If the Interrupt Status
Register is read and the SLIPD bit is a logic 1 then the last slip was due to
the frame buffer becoming full. If the Interrupt Status Register is read and the
SLIPD bit is a logic 0 then the last slip was due to the frame buffer becoming
empty.
SLIPI:
The SLIPI bit is set if a slip occurred since the last read of the Interrupt Status
register. The SLIPI bit is cleared just after the Interrupt Status register read
operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
120
PMC [ PMC-SIERRA, INC ]
