PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register Register 20H: FRMR Frame Alignment Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CRCEN
CASDIS
AFAA
0
0
0
0
0
0
0
0
CHKSEQ
CASA
REFR
REFCRCE
REFRDIS
This register selects the various framing formats and framing algorithms
supported by the FRMR block.
CRCEN:
The CRCEN bit enables the FRMR to frame to the CRC multiframe. When the
CRCEN bit is logic 1, the FRMR searches for CRC multiframe alignment and
monitors for errors in the alignment. A logic 0 in the CRCEN bit position
disables searching for multiframe and suppresses the OOCMF, CRCE,
CMFER, and FEBE FRMR statuses, forcing them to logic 0.
CASDIS:
The CASDIS bit enables the FRMR to frame to the Channel Associated
Signalling multiframe when set to a logic 0. When CAS is enabled, the FRMR
searches for signalling multiframe alignment and monitors for errors in the
alignment. A logic 1 in the CASDIS bit position disables searching for
multiframe and suppresses the OOSMF and the SMFER FRMR outputs,
forcing them to logic 0.
AFAA:
The AFAA bit enables an alternate framing algorithm. If AFAA is a logic zero,
frame alignment is declared after a correct FAS, a logic 1 in bit 2 of time slot
0 of the next frame and finally another FAS in the third frame are found. If one
of the conditions fails, the next bit position is checked for valid framing. If
AFAA is a logic one, the framing is similar to the above, but adds a "hold-off"
feature. If bit2 or the second 7-bit FAS conditions fail, the same byte location
is checked again in the subsequent frames before checking the next bit
position for frame alignment.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
122
PMC [ PMC-SIERRA, INC ]
