PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 21H: FRMR Maintenance Mode Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R
FASC
BIT2C
0
0
0
0
0
0
X
X
SMFASC
T16C
RADEB
RMADEB
CMFACT
EXCRCE
R
FASC:
The FASC bit selects the criterion used to declare loss of frame alignment
signal: a logic 0 in the FASC bit position enables declaration of loss of frame
alignment when 3 consecutive frame alignment patterns have been received
in error; a logic 1 in the FASC bit position enables declaration of loss of frame
when 4 consecutive frame alignment pattern errors are detected.
BIT2C:
The BIT2C bit enables the additional criterion that loss of frame is declared
when bit 2 in time slot 0 of NFAS frames has been received in error on 3
consecutive occasions: a logic 1 in the BIT2C position enables declaration of
loss of frame alignment when bit 2 is received in error; a logic 0 in BIT2C
enables declaration of loss of frame alignment based on the setting of FASC,
only.
SMFASC:
The SMFASC bit selects the criterion used to declare loss of signalling
multiframe alignment signal: a logic 0 in the SMFASC bit position enables
declaration of loss of signalling multiframe alignment when 2 consecutive
multiframe alignment patterns have been received in error; a logic 1 in the
SMFASC bit position enables declaration of loss of signalling multiframe when
2 consecutive multiframe alignment patterns have been received in error or
when time slot 16 contains logic 0 in all bit positions for 1 or 2 multiframes
based on the criterion selected by T16C.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
124
PMC [ PMC-SIERRA, INC ]
