PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
T16C:
The T16C bit selects the criterion used to declare loss of signalling multiframe
alignment signal when enabled by the SMFASC: a logic 0 in the T16C bit
position enables declaration of loss of signalling multiframe alignment when
time slot 16 contains logic 0 in all bit positions for 1 multiframe; a logic 1 in the
T16C bit position enables declaration of loss of signalling multiframe when
time slot 16 contains logic 0 in all bit positions for 2 consecutive signalling
multiframes.
RADEB:
The RADEB bit selects the amount of debouncing applied to the Remote
Alarm Indication before the RRA is allowed to change state: a logic 0 in the
RADEB bit position enables the RRA output to change to the logic value
contained in the Remote Alarm bit position (bit 3 of NFAS frames) when the
received Remote Alarm bit value has been in the same state for 2
consecutive NFAS frames; a logic 1 in the RADEB bit position enables the
RRA output to change when the Remote Alarm bit has been in the same
state for 3 consecutive NFAS frames.
RMADEB:
The RMADEB bit selects the amount of debouncing applied to the Remote
Signalling Multiframe Alarm Indication before the RRMA is allowed to change
state: a logic 0 in the RMADEB bit position enables the RRMA output to
change to the logic value contained in the Remote Signalling Multiframe
Alarm bit position (bit 6 of time slot 16 of frame 0 of the signalling multiframe)
when the received Remote Signalling Multiframe Alarm bit value has been in
the same state for 2 consecutive signalling multiframes; a logic 1 in the
RMADEB bit position enables the RRMA output to change when the Remote
Signalling Multiframe Alarm bit has been in the same state for 3 consecutive
signalling multiframes.
CMFACT:
The CMFACT bit is an active high status bit indicating that the CRC
Multiframe Find algorithm has been active for more than 8ms, thereby
initiating a reframe if the CRCEN bit is set to logic 1. The CMFACT bit is reset
to logic 0 after the register is read.
EXCRCE:
The EXCRCE bit is an active high status bit indicating that excessive CRC
evaluation errors (i.e. ≥915 error in one second) have occurred, thereby
initiating a reframe if enabled by the REFCRCE bit of the Frame Alignment
Options register. The EXCRCE bit is reset to logic 0 after the register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
