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PM6341-QI 参数 Datasheet PDF下载

PM6341-QI图片预览
型号: PM6341-QI
PDF下载: 下载PDF文件 查看货源
内容描述: E1成帧器/收发器 [E1 FRAMER/TRANSCEIVER]
分类和应用: PC
文件页数/大小: 272 页 / 902 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM6341 E1XC  
DATA SHEET  
PMC-910419  
ISSUE 8  
E1 FRAMER/TRANSCEIVER  
OVRE,UNDE:  
The OVRE and UNDE bits control the generation of an interrupt on the  
microprocessor INTB pin when a FIFO error event occurs. When OVRE or  
UNDE is set to logic 1, an overrun event or underrun event, respectively, is  
allowed to generate an interrupt on the INTB pin. When OVRE or UNDE is  
set to logic 0, the FIFO error events are disabled from generating an interrupt.  
SYNC:  
The SYNC bit enables the PLL to synchronize the phase delay between the  
FIFO input and output data to the phase delay between reference clock input  
and smooth output clock at the PLL. For example, if the PLL is operating so  
that the smooth output clock lags the reference clock by 24 UI, then the  
synchronization pulses that the PLL sends to the FIFO will force its output  
data to lag its input data by 24 UI.  
LIMIT:  
The LIMIT bit enables the PLL to limit the jitter attenuation by enabling the  
FIFO to increase or decrease the frequency of the smooth output clock  
whenever the FIFO is within one unit interval (UI) of overflowing or  
underflowing. This limiting of jitter ensures that no data is lost during high  
phase shift conditions. When LIMIT is set to logic 1, the PLL jitter attenuation  
is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally.  
Upon reset of the E1XC, the LIMIT and SYNC bits are set to logic 1, and the  
OVRE, UNDE, and CENT bits are set to logic 0.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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