PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 09H: ReceiveTS0 Data Link Enables
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
SACE
X
0
X
1
0
0
0
0
R/W
R
SACI
R/W
R/W
R/W
R/W
R/W
RXSA4EN
RXSA5EN
RXSA6EN
RXSA7EN
RXSA8EN
SACE:
The SACE bit enables the generation of an interrupt whenever there is a
change in the National bits that are not extracted to form a data link.
Changes in the National bits are not debounced, i.e. the interrupt is generated
immediately when the current value of the National bits differs from the
previous value. The value of the National bits can be read in the FRMR
International/National Bits Register.
SACI:
The SACI bit is set to logic one whenever there is a change in the National
bits that are not extracted to form a data link. The SACI bit is cleared
following a read of this register.
RXSA4EN, RXSA5EN, RXSA6EN, RXSA7EN and RXSA8EN:
The RXSAxEN bits control the extraction of a data link from the received Time
Slot 0 National Use bits (Sa4 through Sa8).
If the RXDMASIG bit is a logic one, the data link bits are terminated by the
internal HDLC receiver; otherwise, the data link is presented on RDLSIG. If
the RXSA4EN is logic 1, the RDLSIG value is extracted from bit 4 of Time
Slot 0 of non-frame alignment signal frames. If the RXSA8EN is logic 1, the
RDLSIG value is extracted from bit 8 of Time Slot 0 of non-frame alignment
signal frames. The other enable bits operate in an analogous fashion. A
clock pulse is generated on RDLCLK for each enable that is logic 1. Any
combination enable bits is allowed resulting in a data rate between 4 kbit/s
and 20 kbit/s.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
91
PMC [ PMC-SIERRA, INC ]
