PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
InputTransmit Bit Settings
Data
XCLK Freq
Effect on Output
Transmit Data
Backplane
transmit data
timed to
HSBPSEL =0
XCLKSEL =0
OCLKSEL1 =0
OCLKSEL0 =0
49.152MHz
TCLKI is a jitter-
free 16.384MHz
clock.TCLKO is
equal to TCLKI÷8.
BTCLK.
PLLREF1
PLLREF0
=X
=X
TCLKISEL =0
SMCLKO =1
XCLKSEL =1
HSBPSEL =0
XCLKSEL =1
OCLKSEL1 =0
OCLKSEL0 =0
16.384MHz
Same as above.
Backplane
transmit data
timed to
jitter-free
16.384MHz
XCLK is a jitter-
free 16.384MHz
clock.TCLKO is
equal to XCLK÷8.
BTCLK.
PLLREF1
PLLREF0
=X
=X
TCLKISEL =1
SMCLKO =1
Upon reset of the E1XC, these bits are cleared to zero, selecting digital jitter
attenuation with TCLKO referenced to the backplane transmit clock, BTCLK.The
following Figure 12 illustrates the various bit setting options, with the reset
condition highlighted.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
88
PMC [ PMC-SIERRA, INC ]
