PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
If all RXSAEN[4:0] bits are set to logic 0, Timeslot 16 is extracted and treated
as a data link. If RXDMASIG is logic 0, Timeslot16 is made available on the
RDLSIG output and RDLCLK is an associated 64 kHz clock. If RXDMASIG is
logic 1, the data link is terminated by the HDLC receiver and the
RDLINT/RDLSIG and RDLEOM/RDLCLK pins operate as a data link interrupt
(RDLINT) and a end-of-message (RDLEOM) indication.
Upon reset of the E1XC, all bits are logic 0 except RXSA4EN. By default, a 4
kbit/s data link is extracted from Sa4 and presented on the RDLSIG output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
92
PMC [ PMC-SIERRA, INC ]
