PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 08H: E1XC Master Interrupt Source
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
DJAT
RSLC
X
X
X
X
X
X
X
X
FRMR/SA
XPLS
ELST
RFDL
XFDL
CDRC
This register allows software to determine the block which produced the interrupt
on the INTB output pin. The FRMR/SA bit is a logic 1 if either the FRMR or the
the SACI bit in the Receive TS0 Data Link Enable register (Register 09H) is the
source of the interrupt.
Reading this register does not remove the interrupt indication; the corresponding
block's interrupt status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
90
PMC [ PMC-SIERRA, INC ]
