PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
either the TCLKI input clock or an internal smooth 2.048MHz clock, as
selected by the OCLKSEL0 bit. When OCLKSEL0 is set to logic 1, the DJAT
FIFO output clock is driven with the TCLKI input clock. When OCLKSEL0 is
set to logic 0, the DJAT FIFO output clock is driven with the internal smooth
2.048 MHz clock selected by the TCLKISEL and SMCLKO bits.
PLLREF1, PLLREF0:
The PLLREF[1:0] bits select the source of the Digital Jitter Attenuator phase
locked loop reference signal as follows:
PLLREF1 PLLREF0 Source of PLL Reference
0
0
Transmit clock used by TRAN ( either the
2.048MHz BTCLK or the 2.048MHz RCLKO, as
selected by BTXCLK)
0
1
1
1
0
1
BTCLK input
RCLKO output
TCLKI input
TCLKISEL,SMCLKO:
The TCLKISEL and SMCLKO bits select the source of the internal smooth
2.048MHz and 16.384MHz output clock signals. When TCLKISEL and
SMCLKO are set to logic 0, the internal 2.048MHz and 16.384MHz clock
signals are driven by the smooth 2.048MHz and 16.384MHz clock sources
generated by DJAT. When TCLKISEL is set to logic 0 and SMCLKO is set to
logic 1, the internal 2.048MHz clock signal is driven by the TCLKI input signal
divided by 8, and the internal 16.384MHz clock signal is driven by the TCLKI
input signal. When TCLKISEL and SMCLKO are set to logic 1, the internal
2.048MHz clock signal is driven by the XCLK input signal divided by 8, and
the internal 16.384MHz clock signal is driven by the XCLK input signal.The
combination of TCLKISEL set to logic 1 and SMCLKO set to logic 0 should
not be used.
The following table illustrates the required bit settings for these various clock
sources to affect the transmitted data:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
85
PMC [ PMC-SIERRA, INC ]
