PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 07H: E1XCTransmitTiming Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
HSBPSEL
XCLKSEL
OCLKSEL1
OCLKSEL0
PLLREF1
PLLREF0
TCLKISEL
SMCLKO
0
0
0
0
0
0
0
0
This register allows software to configure the options of the transmit timing
section.
HSBPSEL:
The HSBPSEL bit selects the source of the high-speed clock used in the
ELST, SIGX and TPSC blocks. This allows the E1XC to interface to higher
rate backplanes (>2.048MHz) that are externally gapped; however, the
instantaneous backplane clock frequency must not exceed 3.0MHz. When
HSBPSEL is set to logic 1, the XCLK input signal is divided by 2 and used as
the high-speed clock to these blocks. XCLK must be driven with 49.152MHz.
When HSBPSEL is set to logic 0, the block high-speed clock is driven with
the internal 16.384MHz clock source selected by the XCLKSEL bit.
XCLKSEL:
The XCLKSEL bit selects the source of the high-speed clock used in the
CDRC, FRMR, and PMON blocks. When XCLKSEL is set to logic 1, the
XCLK input signal is used as the high-speed clock to these blocks. XCLK
must be driven with 16.384MHz. When XCLKSEL is set to logic 0, the block
high-speed clock is driven with the internal DJAT generated smooth
16.384MHz clock source. XCLK must be driven with 49.152MHz.
OCLKSEL1, OCLKSEL0:
The OCLKSEL[1:0] bits select the source of the Digital Jitter Attenuator FIFO
output clock signal. When OCLKSEL1 is set to logic 1, the DJAT FIFO output
clock is driven with the input data clock driving the DJAT ICLK input. In this
mode the jitter attenuation is disabled and the input clock must be jitter-free.
When OCLKSEL1 is set to logic 0, the DJAT FIFO output clock is driven with
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
84
PMC [ PMC-SIERRA, INC ]
